In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of the devices. In recent years, a flip-chip attachment method or a flip-chip direct chip attachment (CA) method has been used in packaging integrated circuit chips. In the flip-chip attachment method, instead of attaching an integrated circuit lead frame in a package, an array of solder balls is formed on the surface of the die for the subsequent bonding to a printed circuit board of or an interposer. The formation of the solder balls can be carried out by an evaporation method utilizing a solder material consisting mainly of tin and lead through a mask to produce the balls in a desired pattern. More recently, the technique of eletrodeposition has also been used to mass produce solder balls in a flip-chip packaging process.
In the flip-hip attachment method, all the interconnections between a semiconductor chip and a printed circuit board (PCB) or an interposer can be formed simultaneously and therefore maximizing fabrication throughputs. For instance, direct chip attachment, solder bumps or solder balls are used to connect a chip directly to a printed circuit board or an interposer. In a regular printed circuit board, the density of the interconnections is not formed high enough to match that normally found on a chip surface. In other words, the pitch between the bond pads formed on a chip is smaller than the pitch formed between interconnections on a printed circuit board. An interposer is therefore used to provide a transition and to accommodate the bond pads/interconnections which are spaced differently. An interposer board is frequently fabricated of the same material as that used in the printed circuit board, i.e., an epoxy-type polymeric material. When a high density interconnect printed circuit board is utilized in a flip-chip method for bonding to a semiconductor chip, the use of the interposer may not be necessary.
The use of organic substrates, or polymeric-base substrates, in printed circuit boards or interposers introduces a new source of problem for the flip-chip bonding of a silicon chip which is significantly inorganic to such substrates. The problem is the mismatch of coefficients of thermal expansion (CTE) between the printed circuit board and the silicon chip. The coefficient of thermal expansion for the printed circuit board material is at least five times that of the silicon material. The extreme mismatch in CTE's between the silicon chip and the organic substrate of the printed circuit board therefore subjects solder joints formed thereinbetween to extremely large thermal strains, which leads to premature failure of the solder connections.
One method proposed for alleviating such thermal strains is the introduction of an encapsulating layer between the silicon chip and the organic substrate. The encapsulating material, known as an underfill, which is typically a silica field epoxy is used to fill the standoff between the printed circuit board and the silicon chip. Since the silicon chip is normally covered, in a final fabrication step, by a polymer passivation/stress buffer layer such as a polyimide film, the underfill forms a bond between the polyimide layer on the chip and the organic substrate of the printed circuit board encapsulating the solder joints.
While the introduction of the underfill layer between a silicon chip and an organic substrate for the printed circuit board has enhanced the thermal shock resistance of a flip-chip assembly, the organic substrate material still has a coefficient of thermal expansion at least twice that of the underfill material. The effect of the CTE mismatch on the interfacial adhesion of polyimide with underfill can be significant and unacceptable.
It is therefore an object of the present invention to provide an integrated circuit package of an IC chip bonded to a substrate made of a high CTE material that does not have the drawbacks or shortcomings of the conventional integrated circuit packages.
It is another object of the present invention to provide an integrated circuit package that has improved bond strength between an IC chip and a printed circuit board with an underfill material encapsulated thereinbetween.
It is a further object of the present invention to provide an integrated circuit package that has improved bond strength formed between an IC chip and an interposer with an underfill material thereinbetween.
It is another further object of the present invention to provide an integrated circuit package by bonding an IC chip to a surface of a printed circuit board or an interposer which is provided with a surface roughness such that the bond strength to an underfill material is improved.
It is still another object of the present invention to provide an integrated circuit package by bonding an IC chip to a printed circuit board or an interposer wherein the surface of the later is roughened by a multiplicity of dimples to achieve improved bonding with an underfill material.
It is yet another object of the present invention to provide an integrated circuit package that has improved bond strength between an IC chip and a printed circuit board or an interposer wherein the surface of the later is provided with a multiplicity of grooves to achieve improving bonding with an underfill material.
It is still another further object of the present invention to provide a method for improving bond strength in a bond form between an IC chip and a substrate by providing a substrate that has a bonding surface with a surface roughness sufficiently great such that a bond strength formed between the roughened surface and an underfill layer is improved by at least 10%.
It is yet another further object of the present invention to provide a method for improving bond strength in a bond formed between an IC chip and a substrate by providing a roughened surface to a printed circuit board or an interposer which is formed by a multiplicity of grooves.